The inventive concept relates generally to electronic memory technologies. More particularly, the inventive concept relates to a semiconductor memory device and a memory system comprising the same.
Semiconductor memories form an important part of many digital logic systems, such as computers and microprocessor-based applications ranging from satellites to consumer electronics. Consequently, advances in the semiconductor memory technologies can have a significant impact on the performance of a wide variety of technologies.
Semiconductor memory devices can be characterized generally as volatile memory devices, which lose stored data when disconnected from power, or nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM), and examples of nonvolatile memory devices include Mask Read-Only Memory (MROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM).
In an effort to improve the storage capacity of certain types of nonvolatile memory devices, researchers have developed nonvolatile memory devices capable of storing more than one bit of data per memory cell. Such memory devices are commonly referred to as multi-level cell (MLC) memory devices or multi-bit memory devices. An example of a nonvolatile memory device storing more than one bit of data per memory cell is flash memory.
One potential drawback of storing multiple bits of data per memory cell is that it may decrease the reliability of stored data. One cause of this decreased reliability in flash memory devices is that increasing the number of bits per memory cell tends to decrease the margins between threshold voltage distributions corresponding to programmed states. Moreover, with the decreased read margins, the memory cells are increasingly susceptible to the effects of various forms of noise and undesirable electrical effects.
As an example, as the margins between threshold voltage distributions decrease, erase disturbance may become a limiting factor in the design of the threshold voltage distributions, as illustrated by the following. A boosting level of program-inhibited memory cells may be determined by a leakage current characteristic, and may vary according to temperature, program bias conditions, and a physical location of a selected word line. Moreover, in a NAND flash memory device, a channel region of a string including a program-inhibited memory cell may be boosted by a word line bias (e.g., a pass voltage and a program voltage) at a floated state. A channel boosting level may be determined by a voltage applied to a word line, a coupling ratio between a word line and a channel, and a leakage current of a channel region. As the boosting level decreases, the erase disturbance may be exacerbated, which can cause a decrease in a margin between an erase state and a lower-most program state. Accordingly, deterioration of the erase disturbance may become a substantial factor of deteriorating the reliability of a nonvolatile memory device.